In a multi-core system having a disturbed shared memory type structure (i.e., a non-uniform memory access type structure or a NUMA type structure), multiple processors are connected to each other via a bus. In the system, in order to perform a processing in parallel to each other at each processor, it is necessary to synchronize the processing between the processors. Various techniques for synchronizing between the processors are proposed. For example, a synchronizing method using a common variable is disclosed in JP-H04-312160 A (corresponding to U.S. Pat. No. 5,528,761). A synchronizing method using a barrier is disclosed in JP-2013-137833 A (corresponding to US 2009/0193228). Further, a synchronizing method using a message in order to effectively process an event, which is generated asynchronously, is described in JP-H07-234841 A.
In the system having the MUMA type structure, when the synchronizing method using the common variable or the barrier is applied to the system, multiple cores accesses the common variable and the barrier resistor. Accordingly, as the number of cores increases, the process efficiency is reduced. Further, since, in the method for synchronizing by sending and receiving the message, a synchronizing control is complicated when the number of cores increases. Similarly, in this case, the processing efficiency is also reduced.